1. Field of the Invention
The present invention relates to an information processing device and particularly, to an I/O bus bridge having an address conversion mechanism for mutually connecting a memory bus and an I/O bus.
2. Description of the Related Art
A conventional bus bridge is disclosed in JPA-08-314850. This conventional bus bridge is connected with a system bus and an I/O bus, included in a computer system, and used for controlling an access between the respective buses. It includes storage means and access control means. When a write-in access is made from the system bus side to an I/O equipment on the I/O bus, the access control means stores the contents of the write-in access into the storage means and releases the system bus if the I/O equipment is in an inaccessible state, and carries out the write-in access to the I/O equipment on the basis of the contents of the write-in access stored in the storage means if the I/O equipment is switched to an accessible state. Another bus bridge of this kind is also disclosed in JPA-09-089257.
However, the conventional bus bridges such as the bus bridges disclosed in the above publication have the following disadvantages.
A first disadvantage resides in that in a transfer operation of a logical address from the I/O device to the memory bus, a large loss may occur when the transfer of the logical address fails because there is not provided any address conversion mechanism for converting the logical address to an address on the memory bus, that is, a physical address. Alternatively, even if an address conversion mechanism is provided, a large loss may still occur when the transfer fails because this mechanism is a simple TLB (Translation Look-aside Buffer) type mechanism. This is because the address conversion mechanism needs a relatively large resource and thus a cost-down requirement generally causes the address conversion mechanism not to be mounted particularly in a low-price device. Further, even when the address conversion mechanism is mounted, it is necessary to look up an address conversion table entry every time the failure occurs, and this loss makes a critical disadvantages in performance in many cases.
Here, the necessity of the address conversion in spite of the risk of the conversion loss will be explained.
First, the I/O bus generally has address lines which are narrower than the memory bus (system bus). Therefore, if it is not modified, it cannot make an access to an upper-class physical address which exceeds an addressing range of the I/O address.
Secondly, if the address conversion mechanism can be managed on a page basis as in the case of a TLB system serving as an address conversion mechanism which is adopted in a microprocessor, the memory access from the I/O device and the TLB page of CPU can be managed as a pair. Accordingly, the management of the TLB of the CPU and the TLB of the I/O device can be unitarily managed, and this provides a high merit in portability to developments of software. Therefore, the address conversion mechanism has been used, particularly in a device to which a large number of I/O devices are connected.
Next, a second disadvantage will be explained.
Considering the operation of a single I/O device in the prior art, an indication of an access to a memory which is carried out at a time has a size which is much larger than the line size of an I/O cache and needs a transfer size of several K bytes or more. However, the line size of the I/O cache is generally set to several tens bytes such as 32 bytes or 64 bytes. Therefore, the bus bridge transfers the I/O cache of several tens bytes over and over again while repetitively making a miss.
However, the size of the entry of the address conversion table is generally set to several K bytes, and thus an address conversion miss occurs at a frequency which is much lower than the I/O cache. Accordingly, there is a large difference between the address conversion miss rate and the I/O cache miss rate in the memory access of the same I/O device. There was a technical theme on how the difference is decreased without largely increasing hardware scale. The reason is as follows. If an address conversion table and an I/O cache are contained on the assumption that the entry number of the address conversion table and the entry number of the I/O cache are set to the same hit rate, an extremely large amount of the entry number of the I/O cache must be prepared. Therefore, there cannot be realistically provided the entry number of the I/O cache which is assumed to have the same hit rate as the address conversion table without increasing hardware scale.
A third disadvantage is as follows. PTE (Page Table Entry) which is TLB-refilled due to I/O-TLB miss is normally smaller than the data size of one loading. As a result, the usage efficiency of the system bus which needs a throughput performance (for example, a multiprocessor bus) may be reduced. Further, when the length of data which are transferred by only one DMA is longer than the page size of I/O-TLB, a miss occurs on a page basis, and the refilling is carried every time such a miss occurs. This may cause deterioration in throughput performance.
A fourth disadvantage is as follows. Devices are classified into two types, one type being directed to a communication/multimedia type device which needs instantaneousness (hereinafter referred to as "latency type device"), and the other type being directed to a device which transfers data at the maximum rate until transfer of data of predetermined transfer bytes is completed once a DMA request is issued(hereinafterreferred to as "throughput type device"). The time interval of the DMA requests from the I/O bus is relatively long. In such a system that plural latency type devices and throughput type devices are connected to a bus bridge, when the plural throughput type devices use I/O-TLB as a logical address - physical address conversion mechanism once they start to operate, the throughput type device temporarily occupy I/O-TLB entry. In this case, even when a latency type device issues a DMA request, a miss necessarily occurs at I/O-TLB. If this state is continued at some times, there would occur such a situation that a prescribed latency performance cannot be satisfied.